Semiconductor Memory Device and Method of Fabricating the Same

ABSTRACT

Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2013-0012523, filed onFeb. 4, 2013, in the Korean Intellectual Property Office, the entirecontents of which are hereby incorporated by reference.

BACKGROUND

Embodiments of the inventive concept relate to a semiconductor deviceand a method of fabricating the same, and in particular, to asemiconductor memory device and a method of fabricating the same.

Highly integrated semiconductor memory devices have increased in demandwith the development of electronic industry. The integration density ofsemiconductor memory devices can be a factor that may influence the costof the semiconductor memory devices. That is, if the integration densityof the semiconductor memory devices increases, the cost of thesemiconductor memory devices may be lowered. The integration density ofsemiconductor memory devices, such as planar semiconductor memorydevices, may be mainly determined by a planar area that a unit memorycell occupies. Accordingly, the integration density of the planarsemiconductor memory devices may be affected by, for example, atechnology for forming fine and small patterns. However, realizing finepatterns in the planar semiconductor memory devices may result inincreasing manufacturing costs and/or high priced apparatuses.Therefore, there may be some limitations in forming the small and finepatterns.

Recently, three dimensional semiconductor devices, including memorycells arranged in a three dimensional array, have been proposed toovercome the above limitations. Nevertheless, new processes which arecapable of reducing bit cost and realizing reliable products are stillrequired for successful mass production of the three dimensionalsemiconductor memory devices.

SUMMARY

Some embodiments of the inventive concept provide simplified fabricatingmethods and memory devices fabricated thereby.

Other embodiments of the inventive concept provide highly-integratedsemiconductor devices and methods of fabricating the same.

According to some embodiments, a method of fabricating a semiconductormemory device may include forming an electrode structure includinginsulating layers and electrode layers alternatingly stacked on asubstrate, forming a channel hole to penetrate the electrode structure,forming a data storage layer on a sidewall of the channel hole, andforming a semiconductor pattern on a sidewall of the data storage layerto be electrically connected to the substrate. The electrode layers maybe metal-silicide layers, and the insulating layers and the electrodelayers may be formed in an in-situ manner using the same depositionsystem.

In some embodiments, the deposition system may include a first chamber,in which the electrode layers may be formed, and a second chamber, inwhich the insulating layers may be formed.

In some embodiments, the first chamber may be a physical vapordeposition (PVD) chamber and the second chamber may be a chemical vapordeposition (CVD) chamber.

In some embodiments, the electrode layers may be formed using ametal-silicide target.

In some embodiments, the electrode layers may be formed using a metaltarget and a silicon target.

In some embodiments, the method may further include, after the formingof the semiconductor pattern, forming a trench penetrating the electrodestructure, and sequentially forming an insulating spacer and a throughelectrode in the trench.

In some embodiments, the method may further include forming ametal-silicide layer between the through electrode and the substrate.

In some embodiments, the method may further include partially removingthe electrode layers exposed by the trench to form first recess regions,and forming conductive patterns in the first recess regions to be incontact with the electrode layers.

In some embodiments, the conductive patterns may include a conductivemetal nitride.

In some embodiments, the method may further include selectively removingthe insulating layers exposed by the trench to form second recessregions, and forming an additional insulating layer defining air gaps inthe second recess regions.

In some embodiments, the forming of the insulating spacer may includeanisotropically etching the additional insulating layer.

According to some embodiments, a semiconductor memory device may includean electrode structure including insulating layers and gate electrodelayers that may be alternatingly stacked on a substrate, data storagelayers and semiconductor patterns sequentially provided in through holespenetrating the electrode structure, a through electrode providedbetween the through holes, and an insulating spacer provided between thethrough electrode and the electrode layers. The gate electrode layersmay include a conductive metal nitride layer in contact with the datastorage layer and a metal-silicide layer in contact with the insulatingspacer.

In some embodiments, the insulating layers may be formed to define airgaps provided therein.

In some embodiments, the insulating layers and the insulating spacer mayinclude the same material.

In some embodiments, the device may further include a metal-silicidelayer between the through electrode and the substrate.

According to some embodiments, a method of fabricating a semiconductormemory device may include forming an electrode structure includinginsulating layers and electrode layers alternatingly stacked on asubstrate in an in-situ manner using the same deposition system. Themethod may also include forming a channel hole to penetrate theelectrode structure and forming a data storage layer on a sidewall ofthe channel hole. The electrode layers may comprise metal-silicidelayers.

In some embodiments, the method may include forming electrode layers ofthe electrode structure comprises a sputtering process using ametal-silicide and/or silicon target. The method may further compriseforming a metal nitride layer between the electrode layers and the datastorage layer.

In some embodiments, the deposition system may comprise a first chamber,in which the electrode layers are formed, and a second chamber, in whichthe insulating layers are formed.

In some embodiments, the method may include transferring the substratebetween the first chamber and the second chamber without substantialbreakage of a vacuum level. The first chamber and the second chamber maybe part of the same vacuum system.

In other embodiments, the first chamber and the second chamber may havedifferent vacuum levels.

In some embodiments, the method may also include performing a firstdeposition process in the first chamber and performing a seconddeposition process in the second chamber, wherein the first and seconddeposition processes are different.

According to some embodiments, the method may include forming asemiconductor pattern on a sidewall of the data storage layer to beelectrically connected to the substrate, forming a trench penetratingthe electrode structure, sequentially forming an insulating spacer and athrough electrode in the trench, and forming a metal-silicide layerbetween the through electrode and the substrate.

According to some embodiments, a method of fabricating a semiconductormemory device may include forming an electrode structure including firstinsulating layers and metal-silicide electrode layers alternatinglystacked on a substrate in an in-situ manner using the same depositionsystem. The insulating layers may be formed in a first chamber of thesame deposition system and the metal-silicide electrode layers areformed in a second chamber of the same deposition system. The method mayalso include forming a channel hole to penetrate the electrode structurethrough to the substrate and forming a trench to penetrate the electrodestructure through to the substrate. The method may further includeremoving the first insulating layers exposed by the channel hole and thetrench to form first recess regions and forming second insulating layersin the first recess regions using a deposition technique providing apoor step coverage property so as to form the second insulating layersin the first recess regions having air gaps.

The method may also include partially removing the electrode layersexposed by the channel hole to form second recess regions, forming ametal-nitride conductive layer in the channel hole and partiallyremoving the metal-nitride conductive layer to form metal-nitrideconductive patterns in the second recess regions, the metal-nitrideconductive patterns to be in contact with the electrode layers. Themethod may include forming a data storage layer on a sidewall of thechannel hole contacting the metal-nitride conductive patterns, forming afirst semiconductor pattern on a sidewall of the data storage layer andforming a second semiconductor pattern on a sidewall of the firstsemiconductor pattern to be electrically connected to the substrate. Themethod may also include sequentially forming an insulating spacer and athrough electrode in the trench and forming a metal-silicide layerbetween the through electrode and the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments will be more clearly understood from the followingbrief description taken in conjunction with the accompanying drawings.The accompanying drawings represent non-limiting, example embodiments asdescribed herein.

FIG. 1 is an equivalent circuit diagram of a semiconductor memory deviceaccording to some embodiments of the inventive concept.

FIG. 2 is a perspective view of a semiconductor memory device accordingto some embodiments of the inventive concept.

FIG. 3 is a flow chart illustrating a method of fabricating asemiconductor memory device, according to some embodiments of theinventive concept.

FIGS. 4 through 9 are sectional views illustrating a method offabricating a semiconductor memory device, according to some embodimentsof the inventive concept.

FIGS. 10 through 12 are sectional views illustrating a semiconductormemory device and a method of fabricating the same, according to otherembodiments of the inventive concept.

FIGS. 13 through 15 are sectional views illustrating a semiconductormemory device and a method of fabricating the same, according to stillother embodiments of the inventive concept.

FIG. 16 is a sectional view illustrating a semiconductor memory deviceand a method of fabricating the same, according to even otherembodiments of the inventive concept.

FIGS. 17 and 18 are perspective views illustrating data storage layersaccording to some embodiments of the inventive concept.

FIG. 19 is a schematic diagram illustrating a deposition apparatus,which may be used to form electrode layers and insulating layers,according to some embodiments of the inventive concept.

FIG. 20 is a schematic block diagram illustrating an example ofelectronic systems including semiconductor memory devices according tosome embodiments of the inventive concept.

FIG. 21 is a schematic block diagram illustrating memory cards includingthe semiconductor devices according to some embodiments of the inventiveconcept.

FIG. 22 is a block diagram illustrating information processing systemsincluding the semiconductor devices according to some embodiments of theinventive concept.

It should be noted that these figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feature.

DETAILED DESCRIPTION

Some embodiments of the inventive concepts will now be described morefully with reference to the accompanying drawings, in which someembodiments are shown. Embodiments of the inventive concepts may,however, be embodied in many different forms and should not be construedas being limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the concept of the embodiments to thoseof ordinary skill in the art. In the drawings, the thicknesses of layersand regions are exaggerated for clarity. Like reference numerals in thedrawings denote like elements, and thus their description will beomitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers indicate like elementsthroughout. As used herein the term “and/or” includes any and allcombinations of one or more of the associated listed items. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon”).

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of the embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit the embodiments. As usedherein, the singular forms “a,” “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”,“comprising”, “includes” and/or “including,” if used herein, specify thepresence of stated features, integers, steps, operations, elementsand/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which embodiments of the inventiveconcepts belong. It will be further understood that terms, such as thosedefined in commonly-used dictionaries, should be interpreted as having ameaning that is consistent with their meaning in the context of therelevant art and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

FIG. 1 is an equivalent circuit diagram of a semiconductor memory deviceaccording to some embodiments of the inventive concept.

Referring to FIG. 1, a semiconductor memory device according to anembodiment may include a common source line CSL, a plurality of bitlines BL0, BL1, BL2 and BL3, and a plurality of cell strings CSTRdisposed between the common source line CSL and the bit lines BL0-BL3.

The common source line CSL may be a conductive layer disposed on asubstrate (e.g., a semiconductor substrate) or an impurity region formedin the substrate. The bit lines BL0-BL3 may be conductive patterns(e.g., metal lines) disposed over the substrate and separated from thesubstrate. The bit lines BL0 to BL3 may be two dimensionally arrayed,and a plurality of cell strings CSTR may be electrically connected inparallel (to one another to each of the bit lines BL0 to BL3. Thus, thecell strings CSTR may be two dimensionally arrayed on the common sourceline CSL or the substrate.

Each of the cell strings CSTR may be configured to include a groundselection transistor GST connected to the common source line CSL, astring selection transistor SST connected to one of the bit linesBL0-BL3, and a plurality of memory cell transistors MCT disposed betweenthe ground selection transistor GST and the string selection transistorSST. The ground selection transistor GST, the plurality of memory celltransistors MCT and the string selection transistor SST constitutingeach of the cell strings CSTR may be serially connected to each other.In addition, gate electrodes of the ground selection transistors GST mayextend to form a ground selection line GSL, and gate electrodes of thestring selection transistors SST may extend to form a plurality ofstring selection lines SSL0, SSL1 and SSL2. Further, gate electrodes ofthe memory cell transistors MCT may extend to form a plurality of wordlines WL0, WL1, WL2 and WL3. The ground selection line GSL, the stringselection lines SSL0 to SSL2 and the word lines WL0 to WL3 may bedisposed between the common source line CSL and the bit lines BL0 toBL3.

The ground selection transistors GST may be located at substantially thesame distance from the substrate, and the gate electrodes of the groundselection transistors GST may be commonly connected to the groundselection line GSL to have the same electrical potential. Accordingly,the ground selection line GSL may be a plate-shaped conductive patternor a comb-shaped conductive pattern which is disposed between the commonsource line CSL and the lowermost memory cell transistors MCT closest tothe common source line CSL. Similarly, the gate electrodes of the memorycell transistors MCT, which are located at the same level from thecommon source line CSL, may also be connected to one of the word linesWL0 to WL 3 to have the same electrical potential. Thus, each of theword lines WL0 to WL3 may be a plate-shaped conductive pattern or acomb-shaped conductive pattern which is parallel with the substrate.Meanwhile, since the memory cell transistors MCT constituting each ofthe cell strings CSTR are located at different levels from one another,the plurality of word lines WL0 to WL3 disposed between the commonsource lines CSL and the bit lines BL0 to BL3 may also be located atdifferent levels from one another. That is, the plurality of word linesWL0 to WL3 may be vertically stacked to form a multi-layered structure.

Each of the cell strings CSTR may include a semiconductor pillar thatvertically extend to be connected to one of the bit lines BL0 to BL3.The semiconductor pillar of each of the cell strings CSTR may penetratethe ground selection line GSL and the word lines WL0 to WL3. Inaddition, the semiconductor pillar of each of the cell strings CSTR mayinclude a body and an impurity region formed in one end of the body.Alternatively, the semiconductor pillar of each of the cell strings CSTRmay include a body and at least one impurity region formed in at leastone end of the body. For example, the semiconductor pillar may include abody and a drain region formed in an upper portion of the body.

A data storage layer may be disposed between the word lines WL0 to WL3and each of the semiconductor pillars. In some embodiments, the datastorage layer may include a charge storage layer. For example, the datastorage layer may be an insulating charge trap layer, a conductivefloating gate, or an insulating layer with conductive nano dots.

A dielectric layer, which acts as a gate insulation layer of the groundselection transistor GST or the string selection transistors SST, may bedisposed between the ground selection line GSL and the semiconductorpillars or between the string selection lines SSL0 to SSL2 and thesemiconductor pillars. The gate insulation layer of the ground selectiontransistor GST and/or the gate insulation layer of the string selectiontransistors SST may be formed of the same material as the data storagelayer of the memory cell transistors MCT. Alternatively, the gateinsulation layer of the ground selection transistor GST and/or the gateinsulation layer of the string selection transistors SST may be formedof a gate oxide layer (e.g., a silicon oxides layer) commonly used in ametal-oxide-semiconductor field effect transistor (MOSFET).

Each of the ground and string selection transistors GST and SST and thememory cell transistors MCT may have a similar structure to the MOSFETthat employs the semiconductor pillar as a channel region. That is,source/drain regions may be disposed in some portions of thesemiconductor pillar, which are located between the ground selectionline GSL, the word lines WL0 to WL3 and the string selection line SSL.Alternatively, the word lines WL0 to WL3 may constitute a plurality ofMOS capacitors together with the semiconductor pillar without anysource/drain regions therebetween. In this case, if a voltage higherthan threshold voltages of the MOS capacitors is applied to the wordlines WL0 to WL3, inversion regions corresponding to the source/drainregions may be formed in the semiconductor pillar between the word linesWL0 to WL3. This may be due to fringing fields. Thus, the memory celltransistors MCT of each of the cell strings CSTR may be electricallyconnected to one another even without formation of the source/drainregions.

FIG. 2 is a perspective view of a semiconductor memory device accordingto some embodiments of the inventive concept.

Referring to FIG. 2, a substrate 100 may be provided. The substrate 100may be one of a silicon wafer, a germanium wafer, or a silicon-germaniumwafer. For example, the substrate 100 may be a wafer doped with p-typedopants. An electrode structure may be provided on the substrate 100.The electrode structure may include insulating layers 120 and aplurality of electrode layers 110 spaced apart from each other in a zdirection by the insulating layers 120. The lowermost one of theelectrode layers 110 may serve as a lower selection gate pattern, andthe uppermost one may serve as an upper selection gate pattern. Gatepatterns between the upper and lower selection gate patterns may serveas cell gate patterns. An insulating buffer layer 105 may be providedbetween the substrate 100 and the lower selection gate pattern to be incontact with the substrate 100. The electrode layers 110 may be formedto have at least two different thicknesses, although illustrated to havethe same thickness. For example, one or all of the lower and upperselection gate patterns may be thicker than each of the cell gatepatterns.

The electrode layers 110 may be metal-silicide layers. For example, theelectrode layers 110 may include at least one of cobalt silicide, nickelsilicide, boron silicide, calcium silicide, cerium silicide, chromiumsilicide, hafnium silicide, molybdenum silicide, niobium silicide,platinum silicide, rhodium silicide, tantalum silicide, titaniumsilicide, tungsten silicide, vanadium silicide, or zirconium silicide.The insulating layers 120 may include at least one of a silicon oxidelayer, a silicon nitride layer, or a silicon oxynitride layer, orinclude an insulating layer, whose dielectric constant is lower thanthat of the silicon oxide layer. The insulating buffer layer 105 mayinclude a silicon oxide layer.

In order to reduce complexity in the drawings and to provide betterunderstanding of some embodiments of the inventive concept, theelectrode layers 110 and the insulating layers 120 were illustrated inFIGS. 2 and 4-16 to have six-layered structure. In addition, the upperand lower selection gate patterns may be provided to have amulti-layered structure.

Channel holes 125 may be formed to expose the substrate 100 through theelectrode structure, and data storage layers DA may be provided onsidewalls of the channel holes 125. The data storage layers DA mayinclude a plurality of insulating layers. For example, the data storagelayers DA may include at least one nitride layer. The data storagelayers DA will be described in more detail with reference to FIGS. 17and 18.

Semiconductor patterns 133 may be provided on sidewalls of the datastorage layers DA and be electrically connected to the substrate 100.The semiconductor patterns 133 may be substantially perpendicular to thetop surface of the substrate 100. Each of the semiconductor patterns 133may include a first semiconductor pattern 131 and a second semiconductorpattern 132 sequentially stacked on the data storage layers DA. Thefirst semiconductor pattern 131 may be provided on a sidewall of thedata storage layer DA to have a spacer shape, and the secondsemiconductor pattern 132 may be connected to the substrate 100 throughthe data storage layer DA. For example, the first and secondsemiconductor patterns 131 and 132 may include at least one of silicon,germanium, or silicon-germanium.

Insulating gap-fill patterns 172 may be provided on the secondsemiconductor patterns 132. For example, the insulating gap-fillpatterns 172 may fill the channel holes 125 provided with the datastorage layers DA and the semiconductor patterns 133. The insulatinggap-fill patterns 172 may include at least one of a silicon oxide layer,a silicon nitride layer, or a silicon oxynitride layer.

A through electrode 185 may be provided between the semiconductorpatterns 133 to extend along y direction. For example, the throughelectrode 185 may be provided in a trench 140. In some embodiments, thethrough electrode 185 may constitute a part of the common source line.For example, the through electrode 185 may include tungsten, titanium,or tantalum. An insulating spacer 182 may be provided between thethrough electrode 185 and the electrode layers 110. The insulatingspacer 182 may separate the electrode layers 110 electrically from thethrough electrode 185. The insulating spacer 182 may extend along asidewall of the through electrode 185. The insulating spacer 182 mayinclude at least one of a silicon oxide layer, a silicon nitride layer,or a silicon oxynitride layer.

A metal-silicide layer 170 may be provided between the through electrode185 and the substrate 100. The metal-silicide layer 170 may contributeto reduce a contact resistance between the through electrode 185 and thesubstrate 100. For example, the metal-silicide layer 170 may include atleast one of tungsten silicide, titanium silicide, or cobalt silicide.

Conductive lines 198 may be provided on the semiconductor patterns 133to be connected to the semiconductor patterns 133, electrically. Theconductive lines 198 may extend along a direction (hereinafter, xdirection) crossing the electrode layers 110. Each of the conductivelines 198 may be electrically connected to a plurality of thesemiconductor patterns 133 arranged along the x direction. Theconductive lines 198 and the semiconductor patterns 133 may beelectrically connected to each other via contact plugs 199. Theconductive lines 198 and the contact plugs 199 may include at least oneof metals, conductive metal nitrides, or doped semiconductor materials.

FIGS. 17 and 18 are perspective views illustrating data storage layersaccording to some embodiments of the inventive concept. The data storagelayers DA may include a charge storing layer CL. The charge storinglayer CL may include one of insulating layers with many trap sites andinsulating layers with nano particles and be formed by one of a chemicalvapor deposition (CVD) or an atomic layer deposition (ALD). For example,the charge storing layer CL may include one of a trap insulating layer,a floating gate electrode, or an insulating layer with conductive nanodots. Alternatively, the charge storing layer CL may include at leastone of a silicon nitride layer, a silicon oxynitride layer, asilicon-rich nitride layer, a nanocrystalline silicon layer, or alaminated trap layer.

The data storage layer DA may include a tunnel insulating layer TILinterposed between the charge storing layer CL and the semiconductorpattern 133. The tunnel insulating layer TIL may include a material,whose bandgap is greater than that of the charge storing layer CL, andbe formed by one of a chemical vapor deposition or an atomic layerdeposition. In some embodiments, the tunnel insulating layer TIL may bea silicon oxide layer, which may be formed using one of the depositiontechniques. Further, a thermal treatment process may be performed on thetunnel insulating layer TIL. The thermal treatment process may be arapid thermal nitridation (RTN) or an annealing process performed underan ambient containing at least one of nitrogen or oxygen.

As shown in FIG. 17, the data storage layer DA may include a firstinsulating blocking layer BIL1 interposed between the charge storinglayer CL and the electrode layers 110. Alternatively, as shown in FIG.18, the data storage layer DA may include a first insulating blockinglayer BIL1 and a second insulating blocking layer BIL2 interposedbetween the charge storing layer CL and the electrode layers 110. Thefirst and second insulating blocking layers BIL1 and BIL2 may be formedof different materials, and one of the first and second insulatingblocking layers BIL1 and BIL2 may have a bandgap that is lower than thatof the tunnel insulating layer TIL and higher than that of the chargestoring layer CL. The first and second insulating blocking layers BIL1and BIL2 may be formed using one of a chemical vapor deposition or anatomic layer deposition, and at least one of them may be formed using awet oxidation process. In some embodiments, the first insulatingblocking layer BIL1 may be one of high-k dielectrics (e.g., aluminumoxide and hafnium oxide), and the second insulating blocking layer BIL2may be a material whose dielectric constant is lower than that of thefirst insulating blocking layer BILL In other embodiments, the secondinsulating blocking layer BIL2 may be one of the high-k dielectrics, andthe first insulating blocking layer BIL1 may be a material, whosedielectric constant is lower than that of the second insulating blockinglayer BIL2.

FIG. 3 is a flow chart illustrating a method of fabricating asemiconductor memory device, according to some embodiments of theinventive concept. FIGS. 4 through 9 are sectional views illustrating amethod of fabricating a semiconductor memory device, according to someembodiments of the inventive concept.

Referring to FIGS. 3 and 4, the electrode layers 110 and the insulatinglayers 120 may be alternatingly and repeatedly stacked on the substrate100 to form an electrode structure (in S1). The electrode layers 110 maybe metal-silicide layers. The substrate 100 may be a semiconductorsubstrate. For example, the substrate 100 may be a silicon wafer, agermanium wafer, a silicon-germanium wafer, or a compound semiconductorwafer. The electrode layers 110 and the insulating layers 120 may beformed in an in-situ manner within the same deposition system.

Here, the in-situ process may include a plurality of process steps thatare performed in a plurality of chambers, respectively, constituting asame vacuum system. In addition, the same vacuum system may refer to acluster of chambers, in which a wafer can be transferred from one toanother without a substantial breakage of a vacuum level. In someembodiments, the chambers may be configured to have different vacuumlevels from each other.

FIG. 19 is a schematic diagram illustrating a deposition apparatus 200,which may be used to form the electrode layers 110 and the insulatinglayers 120, according to some embodiments of the inventive concept. Thedeposition apparatus 200 may include a first chamber 201 and a secondchamber 202. A wafer transporter 205 may be provided between the firstand second chambers 201 and 202 to grasp a wafer W. The electrode layers110 may be formed in a first chamber 201, and the insulating layers 120may be formed in the second chamber 202. The first and second chambers201 and 202 may be chambers constituting the same vacuum system. Forexample, the wafer W may be transported between the first and secondchambers 201 and 202 by the wafer transporter 205, without a substantialbreakage of a vacuum level of the deposition apparatus 200. The firstand second chambers 201 and 202 may be configured to perform depositionprocesses different from each other. For example, the first chamber 201may be configured to perform a PVD process, and the second chamber 202may be configured to perform a CVD process.

The electrode layers 110 may include at least one of cobalt silicide,nickel silicide, boron silicide, calcium silicide, cerium silicide,chromium silicide, hafnium silicide, molybdenum silicide, niobiumsilicide, platinum silicide, rhodium silicide, tantalum silicide,titanium silicide, tungsten silicide, vanadium silicide, or zirconiumsilicide. For example, the electrode layers 110 may be formed by asputtering process, in which a metal-silicide target is used. In otherembodiments, the electrode layers 110 may be formed by a sputteringprocess, in which a metal target and/or a silicon target are used. Theinsulating layers 120 may be formed of a material having an etchselectivity with respect to the electrode layers 110. For example, theinsulating layers 120 may include a silicon oxide layer, a siliconnitride layer, or a silicon oxynitride layer. In other embodiments, theinsulating layers 120 may include an insulating layer, whose dielectricconstant is lower than that of the silicon oxide layer.

The insulating buffer layer 105 may be provided between the lowermostone of the electrode layers 110 and the substrate 100. The insulatingbuffer layer 105 may be a silicon oxide layer. For example, theinsulating buffer layer 105 may be formed by a thermal oxidation processor a CVD process.

Referring to FIGS. 3 and 5, the channel holes 125 may be formed throughthe electrode structure (in S2). The formation of the channel holes 125may include forming a mask pattern 181 on the electrode structure, andperforming an etching process using the same as an etch mask. The maskpattern 181 may be formed of a material having an etch selectivity withrespect to the electrode layers 110 and the insulating layers 120. Forexample, the mask pattern 181 may be formed of a polysilicon-containingmaterial. Layers provided below the mask pattern 181 may be sequentiallyetched using the mask pattern 181 as an etch mask. The etching processmay be performed, for example, at a high temperature of about 150° C. ina plasma manner. Further, the etching process may be performed, forexample, using an etching gas containing Cl₂ and Ar. In otherembodiments, the etching gas may include CF₄/CHF₃, CF₄/Ar, CCl₂NF₃,CF₄/Cl₂, C1 ₂/N₂/C₂F₆, CF₄/O₂, CF₄/CHF₃/Ar, C₂F₆, C₃F₈, C₄F₈/CO, C₅F₈,or CH₂F₂. During the formation of the channel holes 125, the substrate100 may be over-etched to have a recessed top surface.

Referring to FIG. 6, the data storage layer DA and the firstsemiconductor layer 130 may be sequentially formed to cover side andbottom surfaces of the channel holes 125. The first semiconductor layer130 may include at least one of silicon, germanium, orsilicon-germanium. The data storage layer DA and the first semiconductorlayer 130 may be formed in such a way that the channel holes 125 are notcompletely filled with them. The data storage layer DA and the firstsemiconductor layer 130 may be formed by ALD or CVD.

Referring to FIGS. 3 and 7, the first semiconductor layer 130 may bepatterned to form the first semiconductor pattern 131. The formation ofthe first semiconductor pattern 131 may include an etching process, inwhich plasma is anisotropically used. Accordingly, bottom surfaces ofthe data storage layer DA may be etched during the formation of thefirst semiconductor pattern 131, and thus the substrate 100 may beexposed through the data storage layer DA. The etching process may beperformed in such a way that the data storage layer DA is removed from atop surface of the mask pattern 181. After the etching process, thesecond semiconductor pattern 132 and an insulating gap-fill layer 171may be sequentially formed on the resulting structure. The first andsecond semiconductor patterns 131 and 132 may constitute thesemiconductor pattern 133. As a result, the data storage layers DA andthe semiconductor pattern 133 may be formed in the channel holes 125 (inS3). The second semiconductor pattern 132 may extend along a sidewall ofthe first semiconductor pattern 131 and be connected to the substrate100. The second semiconductor pattern 132 may include at least one of,for example, silicon, germanium, or silicon-germanium. The secondsemiconductor pattern 132 and the insulating gap-fill layer 171 mayextend along a top surface of the mask pattern 181. The secondsemiconductor pattern 132 may be formed by, for example, ALD or CVD.

Referring to FIG. 8, an upper portion of the insulating gap-fill layer171 may be removed to form the insulating gap-fill patterns 172. Theformation of the insulating gap-fill patterns 172 may include, forexample, a process of planarizing and/or etching the insulating gap-filllayer 171. The planarization and/or etching process may be performed toremove portions of the second semiconductor pattern 132 disposed outsidethe channel holes 125.

The electrode layers 110 and the insulating layers 120 may be patternedto form the trench 140. The formation of the trench 140 may include ananisotropic etching process. For example, the anisotropic etchingprocess may be performed in substantially the same manner as the processfor forming the channel holes 125. The trench 140 may be formed toexpose sidewalls of the insulating layers 120 and the electrode layers110 and the top surface of the substrate 100.

Referring to FIGS. 3 and 9, the insulating spacer 182 may be formed inthe trench 140. The insulating spacer 182 may be formed by forming aninsulating layer on the resulting structure with the trench 140 andanisotropically etching the insulating layer. Further, the formation ofthe insulating spacer 182 may include a step of exposing the substrate100. The insulating spacer 182 may include at least one of a siliconoxide layer, a silicon nitride layer, or a silicon oxynitride layer.

The through electrode 185 may be formed on the resulting structureprovided with the insulating spacer 182 to fill the trench 140 (in S4).For example, the through electrode 185 may be used to apply a commonsource voltage to the substrate 100. The through electrode 185 mayinclude at least one of, for example, metals, conductive metal nitrides,or doped semiconductor materials. The metal-silicide layer 170 may beformed between the through electrode 185 and the substrate 100. Themetal-silicide layer 170 may contribute to reduce a contact resistancebetween the through electrode 185 and the substrate 100. In someembodiments, the formation of the metal-silicide layer 170 may include athermal treatment process to be performed after the formation of thethrough electrode 185. In other embodiments, the formation of themetal-silicide layer 170 may include forming a metal layer on thesubstrate 100 exposed by the insulating spacer 182 before the formationof the through electrode 185 and then performing a thermal treatment tothe resulting structure. For example, the metal-silicide layer 170 mayinclude tungsten silicide, titanium silicide, or cobalt silicide.

Referring back to FIG. 2, the conductive lines 198 may be formed toconnect the semiconductor patterns 133 to each other. The conductivelines 198 may extend along the x direction and connect the semiconductorpatterns 133 arranged along the x direction to each other. Theconductive lines 198 may include at least one of, for example, metals,conductive metal nitrides, or doped semiconductor materials. The contactplugs 199 may be formed between the conductive lines 198 and thesemiconductor patterns 133.

According to some embodiments of the inventive concept, the electrodestructure with the metal-silicide layers and the insulating layers maybe formed in an in-situ manner. The metal-silicide layers may serve asword lines of a semiconductor memory device. This makes it possible tofabricate a semiconductor memory device, without an additional processfor forming the word lines. Further, since the data storage layer is notprovided between the insulating layers and the metal silicide layers, itis possible to reduce a thickness of the electrode structure and therebyincrease an integration density of the device.

FIGS. 10 through 12 are sectional views illustrating a semiconductormemory device and a method of fabricating the same, according to otherembodiments of the inventive concept. For the sake of brevity, theelements and features of this example that are similar to thosepreviously shown and described will not be described in much furtherdetail.

Referring back to FIG. 5, the electrode layers 110 exposed by thechannel holes 125 may be horizontally recessed to form first recessregions RS1 as shown in FIG. 10. The first recess regions RS1 may beformed by a selective etching process. The formation of the first recessregions RS1 may include horizontally etching the electrode layers 110using an etch recipe having an etch selectivity with respect to theinsulating layers 120. The recessed electrode layers 110_R may havesidewalls recessed from the sidewalls of the insulating layers 120.

Referring to FIG. 11, a conductive layer 115 may be formed in thechannel holes 125 to fill the first recess regions RS1. The conductivelayer 115 may include a conductive metal nitride, such as a titaniumnitride layer, a tantalum nitride layer, or a tungsten nitride layer.The conductive layer 115 may extend from the channel holes 125 to coverthe top surface of the mask pattern 181, and it may be formed not tofill completely the channel holes 125. The conductive layer 115 may beformed by, for example, a sputtering process.

Referring to FIG. 12, the conductive layer 115 may be etched-back toform conductive patterns 116 in the first recess regions RS1. Forexample, the sidewalls of the insulating layers 120 may be exposed bythe etch-back process. Each conductive pattern 116 and each recessedelectrode layer 110_R that are in contact with each other may constitutea gate electrode.

The process described with reference to FIGS. 6 through 9 may beperformed to the resulting structure provided with the conductivepatterns 116. Accordingly, the data storage layer DA, the semiconductorpattern 133, and the insulating gap-fill pattern 172 may be sequentiallyformed in each of the channel holes 125, and the through electrode 185may be connected to the substrate 100 through the recessed electrodelayers 110_R. In addition, the insulating spacer 182 may be formedbetween the through electrode 185 and the recessed electrode layers110_R, and the metal-silicide layer 170 may be formed between thethrough electrode 185 and the substrate 100. The recessed electrodelayers 110_R may be in contact with the insulating spacer 182, and theconductive patterns 116 may be in contact with the data storage layersDA.

FIGS. 13 through 15 are sectional views illustrating a semiconductormemory device and a method of fabricating the same, according to stillother embodiments of the inventive concept. For the sake of brevity, theelements and features of this example that are similar to thosepreviously shown and described will not be described in much furtherdetail.

Referring back to FIG. 8, the insulating layers 120 may be selectivelyremoved to form second recess regions RS2 as shown in FIG. 13. In thefollowing description to explain the present embodiment, the insulatinglayers 120 will be referred to as the first insulating layers 120. Theuppermost one 120 u of the first insulating layers 120 may include amaterial having an etch selectivity with respect to the others of thefirst insulating layers 120. For example, the uppermost insulating layer120 u may include a silicon oxide layer, and the others may include asilicon nitride layer. In this case, the first insulating layers 120,except for the uppermost insulating layer 120 u, may be selectivelyremoved by an etchant containing phosphoric acid (H₃PO₄). The insulatingbuffer layer 105 may include the same material as the uppermostinsulating layer 120 u.

Referring to FIG. 14, a second insulating layer 183 may be formed in thesecond recess regions RS2. The second insulating layer 183 may includean oxide layer, which may be formed using a deposition techniqueproviding a poor step coverage property. This makes it possible to formair gaps AG in the second recess regions RS2. In some embodiments, theair gaps AG may be formed in all of the second recess regions RS2, asshown in FIG. 14. In other embodiments, the air gaps AG may be formed insome of the second recess regions RS2 and not in the others.

The second insulating layer 183 may be formed to cover the sidewall ofthe trench 140 or the sidewalls of the electrode layers 110. The secondinsulating layer 183 may be formed by forming an insulating layer tocover the electrode structure and anisotropically etching the insulatinglayer to expose the uppermost insulating layer 120 u. As the result ofthe anisotropic etching, the top surface of the substrate 100 in thetrench 140 may be exposed.

Referring to FIG. 15, the through electrode 185 may be formed to fillthe trench 140. In some embodiments, the through electrode 185 mayinclude at least one of, for example, metals, conductive metal nitrides,or doped semiconductor materials. The metal-silicide layer 170 may beformed between the through electrode 185 and the substrate 100. Themetal-silicide layer 170 may contribute to reduce the contact resistancebetween the through electrode 185 and the substrate 100. Themetal-silicide layer 170 may include, for example, tungsten silicide,titanium silicide, or cobalt silicide.

FIG. 16 is a sectional view illustrating a semiconductor memory deviceand a method of fabricating the same, according to even otherembodiments of the inventive concept. For the sake of brevity, theelements and features of this example that are similar to thosepreviously shown and described will not be described in much furtherdetail.

The semiconductor memory device of FIG. 16 may be formed by performingthe process described with reference to FIGS. 13 through 15, before theformation of the insulating spacer 182 of FIG. 12. Accordingly, theconductive patterns 116 may be formed to be in contact with the recessedelectrode layers 110_R, and the second insulating layer 183 with the airgaps AG may be formed between the recessed electrode layers 110_R.

FIG. 20 is a schematic block diagram illustrating an example ofelectronic systems including semiconductor memory devices according tosome embodiments of the inventive concept.

Referring to FIG. 20, an electronic system 1100 may be applied to apersonal digital assistant (PDA), a portable computer, a web tablet, awireless phone, a mobile phone, a digital music player or a memory card.The electronic system 1100 may also be applied to another electronicproduct that receives or transmits information data by wireless.

The electronic system 1100 may include a controller 1110, aninput/output (I/O) unit 1120, a memory device 1130, an interface unit1140 and a data bus 1150. At least two of the controller 1110, the I/Ounit 1120, the memory device 1130 and the interface unit 1140 maycommunicate with each other through the data bus 1150. That is, the databus 1150 may correspond to a path through which electrical signals aretransmitted.

The controller 1110 may include at least one of a microprocessor, adigital signal processor (DSP), a microcontroller and the like. Thememory device 1130 may store commands executed by the controller 1110.The I/O unit 1120 may receive data or signals from an external device ormay transmit data or signals to the external device. The I/O unit 1120may include a keypad, a keyboard or a display unit.

The memory device 1130 may include at least one of the semiconductormemory devices according to the exemplary embodiments described above.Alternatively, the memory device 1130 may include another type ofsemiconductor memory device which is different from the semiconductormemory devices described in the above embodiments. For example, thememory device 1130 may include a magnetic memory device, a phase changememory device, a dynamic random access memory (DRAM) device and/or astatic random access memory (SRAM) device.

The interface unit 1140 may transmit electrical data to a communicationnetwork or may receive electrical data from the communication network.

FIG. 21 is a schematic block diagram illustrating memory cards includingthe semiconductor devices according to some embodiments of the inventiveconcept.

Referring to FIG. 21, a memory card 1200 may include a flash memorydevice 1210 having at least one of the semiconductor memory devicesaccording to the exemplary embodiments described above. The memory card1200 may be used as a data storage media for storing a large capacity ofdata. The memory card 1200 may further include a memory controller 1220that controls data communication between a host and the flash memorydevice 1210.

The memory controller 1220 may include a static random access memory(SRAM) device 1221, a central processing unit (CPU) 1222, a hostinterface unit 1223, an error check and correction (ECC) block 1224 anda memory interface unit 1225. The SRAM device 1221 may be used as anoperation memory of the CPU 1222. The host interface unit 1223 may beconfigured to include a data communication protocol between the memorycard 1200 and the host. The ECC block 1224 may detect and correct errorsof data which are read out from the flash memory device 1210. The memoryinterface unit 1225 may connect the memory controller 1220 to the flashmemory device 1210. The central processing unit (CPU) 1222 may controloverall operations for data communication of the memory controller 1220.The memory card 1200 may further include a read only memory (ROM) devicethat stores code data to interface with the host.

FIG. 22 is a block diagram illustrating information processing systemsincluding the semiconductor devices according to some embodiments of theinventive concept.

Referring to FIG. 22, an information processing system 1300 may be amobile system, a desk top computer or the like. The informationprocessing system 1300 may include a flash memory unit 1310 having atleast one of the flash memory devices according to the exemplaryembodiments described above. The information processing system 1300 mayfurther include a modulator-demodulator (MODEM) 1320, a centralprocessing unit (CPU) 1330, a random access memory (RAM) device 1340 anda user interface unit 1350. At least two of the flash memory unit 1310,the MODEM 1320, the CPU 1330, the RAM device 1340 and the user interfaceunit 1350 may communicate with each other through a data bus 1360. Theflash memory unit 1310 may have substantially the same configuration asthe memory card 1200 illustrated in FIG. 22. That is, the flash memoryunit 1310 may include a flash memory device 1311 and a memory controller1312 that controls overall operations of the flash memory device 1311.The flash memory unit 1310 may store data processed by the CPU 1330 ordata transmitted from an external system. The flash memory unit 1310 maybe configured to include a solid state disk. In this case, theinformation processing system 1300 may stably and reliably store theflash memory unit 1310 with a large capacity of data. If the reliabilityof the flash memory unit 1310 is improved, the information processingsystem 1300 may save sources that are required to check and correctdata. As a result, the information processing system 1300 may providefast data communication. The information processing system 1300 mayfurther include a camera image processor, an application chipset and/oran input/output unit.

The semiconductor memory devices according to the exemplary embodimentsdescribed above may be encapsulated using various packaging techniques.For example, the semiconductor memory devices according to theaforementioned exemplary embodiments may be encapsulated using any oneof a package on package (POP) technique, a ball grid arrays (BGAs)technique, a chip scale packages (CSPs) technique, a plastic leaded chipcarrier (PLCC) technique, a plastic dual in-line package (PDIP)technique, a die in waffle pack technique, a die in wafer formtechnique, a chip on board (COB) technique, a ceramic dual in-linepackage (CERDIP) technique, a plastic quad flat package (PQFP)technique, a thin quad flat package (TQFP) technique, a small outlinepackage (SOIC) technique, a shrink small outline package (SSOP)technique, a thin small outline package (TSOP) technique, a system inpackage (SIP) technique, a multi chip package (MCP) technique, awafer-level fabricated package (WFP) technique and a wafer-levelprocessed stack package (WSP) technique.

According to some embodiments of the inventive concept, it is possibleto form an electrode structure including insulating layers and metalsilicide layers in an in-situ manner.

According to other embodiments of the inventive concept, it is possibleto provide a semiconductor memory device with high density.

While some embodiments of the inventive concepts have been particularlyshown and described, it will be understood by one of ordinary skill inthe art that variations in form and detail may be made therein withoutdeparting from the spirit and scope of the attached claims.

1. A method of fabricating a semiconductor memory device, comprising:forming an electrode structure including insulating layers and electrodelayers alternatingly stacked on a substrate; forming a channel hole topenetrate the electrode structure; forming a data storage layer on asidewall of the channel hole; and forming a semiconductor pattern on asidewall of the data storage layer to be electrically connected to thesubstrate, wherein the electrode layers are metal-silicide layers, andthe insulating layers and the electrode layers are formed in an in-situmanner using the same deposition system.
 2. The method of claim 1,wherein the deposition system comprises a first chamber, in which theelectrode layers are formed, and a second chamber, in which theinsulating layers are formed.
 3. The method of claim 2, wherein thefirst chamber is a PVD chamber and the second chamber is a CVD chamber.4. The method of claim 3, wherein the electrode layers are formed usinga metal-silicide target.
 5. The method of claim 3, wherein the electrodelayers are formed using a metal target and a silicon target.
 6. Themethod of claim 1, further comprising, after the forming of thesemiconductor pattern: forming a trench penetrating the electrodestructure; and sequentially forming an insulating spacer and a throughelectrode in the trench.
 7. The method of claim 6, further comprisingforming a metal-silicide layer between the through electrode and thesubstrate.
 8. The method of claim 6, further comprising: partiallyremoving the electrode layers exposed by the trench to form first recessregions; and forming conductive patterns in the first recess regions tobe in contact with the electrode layers.
 9. The method of claim 8,wherein the conductive patterns comprises a conductive metal nitride.10. The method of claim 6, further comprising: selectively removing theinsulating layers exposed by the trench to form second recess regions;and forming an additional insulating layer defining air gaps in thesecond recess regions.
 11. The method of claim 10, wherein the formingof the insulating spacer comprises anisotropically etching theadditional insulating layer. 12.-15. (canceled)
 16. A method offabricating a semiconductor memory device, comprising: forming, in anin-situ manner using a same deposition system, an electrode structurecomprising insulating layers and electrode layers alternatingly stackedon a substrate; forming a channel hole to penetrate the electrodestructure; and forming a data storage layer on a sidewall of the channelhole, wherein the electrode layers comprise metal-silicide layers. 17.The method of claim 16, wherein forming the electrode layers comprises asputtering process using a metal-silicide and/or silicon target, andwherein the method further comprises forming a metal nitride layerbetween the electrode layers and the data storage layer.
 18. The methodof claim 16, wherein the deposition system comprises a first chamber, inwhich the electrode layers are formed, and a second chamber, in whichthe insulating layers are formed.
 19. The method of claim 18, whereinthe first chamber and the second chamber are part of a same vacuumsystem, and wherein forming an electrode structure comprises:transferring the substrate between the first chamber and the secondchamber without substantial breakage of a vacuum level.
 20. The methodof claim 18, wherein the first chamber and the second chamber havedifferent vacuum levels.
 21. The method of claim 18, further comprising:performing a first deposition process in the first chamber to form eachelectrode layer; and performing a second deposition process in thesecond chamber to form each insulating layer, wherein the first andsecond deposition processes are different.
 22. The method of claim 16,further comprising: forming a semiconductor pattern on a sidewall of thedata storage layer to be electrically connected to the substrate;forming a trench penetrating the electrode structure; sequentiallyforming an insulating spacer and a through electrode in the trench; andforming a metal-silicide layer between the through electrode and thesubstrate.
 23. A method of fabricating a semiconductor memory device,comprising: forming, in an in-situ manner using a same depositionsystem, an electrode structure comprising first insulating layers andmetal-silicide electrode layers alternatingly stacked on a substrate,wherein the insulating layers are formed in a first chamber of the samedeposition system and the metal-silicide electrode layers are formed ina second chamber of the same deposition system; forming a channel holeto penetrate the electrode structure through to the substrate; forming atrench to penetrate the electrode structure through to the substrate;removing the first insulating layers exposed by the channel hole and thetrench to form first recess regions; forming second insulating layers inthe first recess regions using a deposition technique providing a stepcoverage property such that the second insulating layers in the firstrecess regions have air gaps; partially removing the electrode layersexposed by the channel hole to form second recess regions; forming ametal-nitride conductive layer in the channel hole; partially removingthe metal-nitride conductive layer to form metal-nitride conductivepatterns in the second recess regions, the metal-nitride conductivepatterns contacting the electrode layers; forming a data storage layeron a sidewall of the channel hole to be in contact with themetal-nitride conductive patterns; forming a first semiconductor patternon a sidewall of the data storage layer; forming a second semiconductorpattern on a sidewall of the first semiconductor pattern to beelectrically connected to the substrate; sequentially forming aninsulating spacer and a through electrode in the trench; and forming ametal-silicide layer between the through electrode and the substrate.